1. Field of the Invention
The present invention relates generally to neural network output selector devices, and more specifically to a device and method for selecting within a group of analog signals the one with the lowest or with the highest value.
2. Description of the Related Art
As known, the majority of these devices, which are known in the literature as xe2x80x9cWinner Take Allxe2x80x9d (WTA) circuits or as xe2x80x9cLoser Take Allxe2x80x9d (LTA) circuits, are provided by means of architectures which exhibit a voltage-follower configuration and make use of inhibitor mechanisms operating among the calculation elements included in them.
A first known technical solution is described in the article xe2x80x9cWinner Take All Networks of O(N) Complexity,xe2x80x9d J. Lazzaro et al., Neural Inform Proc. Syst. 1:703-711, Denver, Colo., 1989, and calls for the use of a selector device comprising a plurality of circuit branches operating in parallel and each including a first voltage follower transistor T1i and a second local positive feedback transistor T2i, where i=1, . . . j, . . . n. The device also comprises a total feedback line LN common to all the circuit branches. Operation of the selector device is as follows. Each circuit branch receives the input of a one-way current Ii and supplies output of a voltage Vi which represents the result of the selection process. When the current Ii=max (I1, . . . In), the voltage Vi coincides with a logarithmic function of Ii, and if the current Ij less than  less than Ii, the voltage Vjxcx9c0. Although advantageous in some ways, this first solution exhibits diverse shortcomings. Indeed, the device does not provide any offset compensation and has a calculation time which depends on the number of elements making it up.
A second known technical solution is described in the article xe2x80x9cA Scalable High-Speed Current-Mode Winner Take All Network for VLSI Neural Applications,xe2x80x9d Sean Smedley et al., IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications 42(5), 1995 which proposes a tree-structured circuit comprising a plurality of cells provided by using bipolar transistors integrated with a BICMOS technology. Each cell receives at input two current signals I1 and I2 which are compared with each other to select the highest one. The latter represents the input for a cell included in a subsequent layer of the tree structure and so on until there is obtained at output the higher input current signal.
A third technical solution is disclosed in U.S. Pat. No. 5,905,387 (xe2x80x9cthe ""387 patentxe2x80x9d) issued on May 18, 1999, to Chinosi, et al, and entitled xe2x80x9cANALOG VOLTAGE-SIGNAL SELECTOR DEVICExe2x80x9d, the disclosure of which is incorporated herein by reference. Chinosi""s approach has significant advantages in speed and flexibility. A circuit which has improved speed and power consumption characteristics beyond those of the ""387 patent is preferred.
In accordance with one aspect of the present invention, the output-selector employs a differential amplifier configuration with a plurality of analog voltage inputs and an analog comparison voltage input. The output selector also employs a logic circuit. The output-selector determines which of the plurality of analog input voltages has the lowest potential. In another aspect of the present invention, the output-selector determines which of the plurality of analog input voltages has the highest potential.